AWS wellarchitected documentation change
Summary
Updated documentation formatting, navigation links, and technical details about IoT device considerations. Changes include header capitalization, hyphenation fixes, indentation adjustments, and additions about connectivity protocols/core architecture details.
Security assessment
The changes primarily focus on formatting improvements and technical clarifications. While there is a mention of 'crypto-accelerators' (hyphen added) and a new bullet point about connectivity protocols, these do not explicitly address new security vulnerabilities or introduce security-specific documentation. The crypto-accelerator reference maintains existing security context without adding new guidance.
Diff
diff --git a/wellarchitected/latest/iot-lens/considerations-for-general-purpose-iot-devices.md b/wellarchitected/latest/iot-lens/considerations-for-general-purpose-iot-devices.md index fadf7c440..fc7e50107 100644 --- a//wellarchitected/latest/iot-lens/considerations-for-general-purpose-iot-devices.md +++ b//wellarchitected/latest/iot-lens/considerations-for-general-purpose-iot-devices.md @@ -3 +3 @@ -[Documentation](/index.html)[AWS Well-Architected](https://aws.amazon.com/architecture/well-architected/)[AWS Well-Architected Framework](abstract-and-introduction.html) +[Documentation](/index.html)[AWS Well-Architected](https://aws.amazon.com/architecture/well-architected/)[AWS Well-Architected Framework](iot-lens.html) @@ -5 +5 @@ -# Considerations for general purpose IoT devices +# Considerations for General Purpose IoT Devices @@ -7 +7 @@ -For general purpose IoT devices, the application and use case will determine the choice between microcontroller (MCU) and microprocessor (MPU). MCU devices are typically designed for low-power, resource-constrained applications. MPU class devices are designed for applications that require higher computational power, multitasking, and higher-level services provided by more capable operating systems. +For general purpose IoT devices, the application and use case will determine the choice between microcontroller (MCU) and microprocessor (MPU). MCU devices are typically designed for low-power, often autonomously battery-operated, and resource constrained applications. MPU class devices are designed for applications that require higher computational power, multitasking, and higher-level services provided by more capable operating systems. @@ -13 +13 @@ For MCU devices, there are several features that can contribute to improved ener -This should include a mode that retains volatile memory content, allowing for quick restoration of application state when required. + * This should include a mode that retains volatile memory content, allowing for quick restoration of application state when required. @@ -15 +15 @@ This should include a mode that retains volatile memory content, allowing for qu - * A Real-Time Clock (RTC) to wake up the device from a low power mode only when needed. + * A Real-Time Clock (RTC) to wake-up the device from a low power mode only when needed. @@ -17 +17 @@ This should include a mode that retains volatile memory content, allowing for qu - * On-chip or on-board crypto accelerators to enable secure communication while minimizing energy consumption. + * On-chip or on-board crypto-accelerators to enable secure communication while minimizing energy consumption. @@ -20,0 +21,2 @@ This should include a mode that retains volatile memory content, allowing for qu + * Connectivity module should utilize quick reconnect protocols + @@ -26 +28 @@ This should include a mode that retains volatile memory content, allowing for qu -Similar criteria also apply to the selection of MPUs, though there are differences. Some MPUs use a combination of high-performance and low-power cores, such as those using the [Arm big.LITTLE](https://www.arm.com/technologies/big-little) architecture. In such architectures, ensure that tasks are assigned to the appropriate core based on the workload. This reduces power consumption while maintaining sufficient processing capabilities. The [FreeRTOS](https://freertos.org/) operating system can take advantage of this architecture through Asymmetric Multiprocessing (AMP). Each core runs an instance of FreeRTOS and communicates through shared memory space and interprocess communication (IPC). The smaller core can be assigned to run non-intensive applications and the large core can be put into low-power mode until needed for more compute intensive tasks. +Similar criteria also apply to the selection of MPUs, though there are differences. Some MPUs utilize a combination of high-performance and low-power cores, such as those using the [big.LITTLE](https://www.arm.com/technologies/big-little) architecture. In such architectures, make surethat tasks are assigned to the appropriate core based on the workload. This reduces power consumption while maintaining sufficient processing capabilities. The [FreeRTOS](https://freertos.org/) operating system can take advantage of this architecture through Asymmetric Multiprocessing (AMP). Each core runs an instance of FreeRTOS and communicates through shared memory space and inter-process communication (IPC). The smaller core can be assigned to run non-intensive applications and the big core can be put into low-power mode until needed for more compute intensive tasks.